Prof. Uri Weiser

The Application Tsunami and the Inevitable Path to Per-Application Tuning

Webinar by Prof. Uri C. Weiser


In the past, we had exponential growth in computing system performance following Moore’s law. As processors became larger and more complex, it became harder to achieve performance growth at the same rate. In parallel, we witness a tsunami of applications in recent years: machine learning, AI, computer vision, data storage, e-commerce, and others, each with its own characteristics. No one rigid solution fits all applications and usage patterns. This led us to an inevitable path in which modern hardware and software are required to be flexible enough to be an almost-perfect-fit for every major application.

In this webinar, Prof. Uri Weiser will share his view on how we got here, the inevitable path to flexible architectures, and the implications.

Presenter bio: Uri Weiser is the Chief Science Officer of Concertio, and is a Professor emeritus at the Electrical Engineering department, the Technion IIT., Haifa Israel. Prof. Weiser worked at Intel from 1988 till 2007, where he initiated the definition of the first Pentium® processor, drove the definition of Intel’s MMX™ technology, co-invented the Trace Cache, co-managed the new Intel Microprocessor Design Center at Austin, Texas and formed an Advanced Media applications research activity. Weiser was appointed an Intel Fellow in 1996, in 2002 he became an IEEE Fellow and in 2005 an ACM Fellow. Prof. Weiser was awarded the ChipEx Global Industry leader award in 2016 and the ACM/IEE prestigious Eckert Mauchly award in 2016. Prior to his career at Intel, Prof. Weiser led the design of the NS32532 microprocessor at National Semiconductor.
Professor Weiser published more than 60 papers, has issued 16 patents, and was an invited speaker at more than 100 Univ/conferences/workshops/industries. He was also an Associate Editor of IEEEMicro Magazine and was Associate Editor of Computer Architecture Letters.

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